Xinje XL Series - 4-6-5 Increment [INC, DINC, QINC] & Decrement [DEC

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 If the value of the divisor is 0, the instruction will be error.
 The highest bit of the result and remainder is the symbol bit (positive:0, negative: 1). When
any of the dividend or the divisor is negative, then the result will be negative. When the
dividend is negative, then the remainder will be negative.
<64 bits operation>
 The dividend is composed by the device appointed by S1 and the next one. The divisor is
composed by the device appointed by S2 and the next one. The result and the remainder are
stored in the four sequential devices, the first one is appointed by D.
 If the value of the divisor is 0, the instruction will be error.
 The highest bit of the result and remainder is the symbol bit (positive:0, negative: 1). When
any of the dividend or the divisor is negative, then the result will be negative. When the
dividend is negative, then the remainder will be negative.
 Note: The addresses of the operands in the QDIV instruction must be even.
4-6-5 Increment [INC, DINC, QINC] & Decrement [DEC, DDEC, QDEC]
1) Summary
Increase or decrease the number
Increase one [INC,DINC,QINC]
16 bits
INC
32 bits
DINC
Execution
condition
Normally ON/OFF,
rising/falling edge
Suitable
Models
XD, XL
Hardware
requirement
-
Software
requirement
-
64 bits
QINC
Execution
condition
Normal ON/OFF/falling or
rising pulse edge
Suitable
Models
XDH, XLH
Hardware
requirement
Version V3.7.1 or later
Software
requirement
Version V3.7.4a or later
Decrease one [DEC,DDEC,QDEC]
16 bits
DEC
32 bits
DDEC
Execution
condition
Normally ON/OFF,
rising/falling edge
Suitable
Models
XD, XL
Hardware
requirement
-
Software
requirement
-
Dividend Divisor Result Remainder
BIN BIN BIN BIN
(D3,D2,D1,D0) ÷ (D7,D6,D5,D4) → (D11,D10,D9,D8) ┅ (D15,D14,D13,D12)
64 bit 64 bits 64 bits 64 bits
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