Xinje XL Series - 4-9-6 Floating Division[EDIV,EDDIV]

175
<64 bits operation>
 The floating value of S1 is multiplied with the floating value point value of S2. The result of
the multiplication is stored at D as a floating value.
 If a constant K or H used as source data, the value is converted to floating point before the
multiplication operation.
 The registers in EDMUL must start with an even address.
<32 bits operation>
EMUL D100K100 D110
X1
<64 bits operation>
Note: the operand value must be floating numbers, otherwise the result will be error.
4-9-6 Floating Division[EDIV,EDDIV]
1) Summary
Floating Divide [EDIV, EDDIV]
16 bits
-
32 bits
EDIV
Execution
condition
Normally ON/OFF,
rising/falling edge
Suitable
Models
XD, XL
Hardware
requirement
-
Software
requirement
-
64 bits
EDDIV
Execution
condition
Normal ON/OFF/falling or
rising pulse edge
Execution
condition
Normal ON/OFF/falling or
rising pulse edge
(K100)× (D101,D100)→ (D111,D110)
Binary converts to Floating Binary Floating Binary Floating
(D13, D12,D11, D10)×(D23, D22,D21, D20)→(D53, D52,D51, D50)
Binary Floating Binary Floating Binary Floating
(K00)
×
(D103, D102,D101, D100)
→
(D113, D112,D111, D110)
Binary converts Binary Floating Binary Floating
to Floating
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