YASKAWA JEPMC-CP3201-E - Page 157

3.3 Multi-CPU Functions
Sub CPU Synchronization
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3
CPU Unit Functionality
Sub CPU Synchronization Data Transfer Timing
This section describes the timing of data transfer for the CPU interface registers for the high-speed and
low-speed scans.
 CPU Interface Registers for High-speed Scan
The following figures show the data transfer timing for CPU interface registers for the high-speed scans.
 When the Main CPU Unit and Sub CPU Unit Have the Same High-speed Scan Set Values
 When High-speed Scan Set Value of Main CPU Unit Is An Integral Multiple of High-speed
Scan Set Value of Sub CPU Unit
 CPU Interface Registers for Low-speed Scan
The low-speed scans are not synchronized, so data transfer for the CPU interface registers for the low-
speed scans is not performed periodically in the way it is for the high-speed scans. However, the Sub CPU
Unit will never read the low-speed scan data that is being transferred from the Main CPU Unit during its
current low-speed scan. Also, the Main CPU Unit will never read the low-speed scan data that is being
transferred from the Sub CPU Unit during its current low-speed scan. In other words, exclusive control is
performed for the data to ensure data concurrency.
  
DWG.H
DWG.H
High-speed
scan of
Main CPU
Unit (4 ms)
High-speed
scan of Sub
CPU Unit
(4 ms)
Output values from
 transferred to
Sub CPU Unit.
Output values from Sub
CPU Unit transferred to .
DWG.H
DWG.H

High-speed
scan of
Main CPU
Unit (4 ms)
High-speed
scan of Sub
CPU Unit
(2 ms)
Output values from
 transferred to
Sub CPU Unit.
Output values from Sub
CPU Unit transferred to .