YASKAWA YASNAC J50

(3) Invert Process
Logic can be set to “ 1” by shofi-pin SW2 settingofFC810, FC860, FC861 when the input contact is “closed” disregarding whether common
OV or 24V is used.
The following shows the inverted bit areas in the common status of each board,
Table A.4 Inverted Bit Area
Common
Connector
Terminal
COM 30
COM 31
COM 32
FC810/FC860 INterval Area
Area No.1 - Area No. 2
Area No. 3 Area No. 4
#looo , #lool
#1016 , #1017 #1032, #1033 #1048, #1049
#loo2, #loo3
#1018, #1019 #lo34 , #lo35 #lo50, #lo51
#loo4
#loo4 #loo4 #loo4
COM 40 #1005, #1006
#lo21, #lo22 #1037, #1038 #lo53, #lo54
COM 41 #1007, #1008
#1023, #1024 #lo39, #lo40 #1055,#1056
COM 42 #loo9
#loo4 #loo4 #loo4
COM 20 #lolo, #loll
#1026, #1027 #1042, #1043 #1058, #1059
COM
21
COM 10
#lo12
#1028 #1044 #1060
#lo13
#1029 #lo45 #1061
Table A.5 Inverted Bit Area
Common
Connector
Terminal
FC
810/FC 860 Inverted Area
Area No.1-1
I Area No. 1-2 \ Area No. 2-1 I Area No. 2-2
COM 00 #looo, #lool
#1008, #1009
#1016, #1017 #1024, #1025
COM 01 #loo2
#lolo #1018 #1026
COM 02
#loo3, #loo4
#loll, #lo12 #1019 , #1020 #1027, #1028
COM 03
#loo5
#lo13
#lo21 #1029
COM 04 #1006, #1007
#lo14, #lo15
#1022, #1023 #lo30, #lo31
Area No. 3-1
Area No. 3-2 Area No. 4-1
Area No. 4-2
COM 00
#1032, #1033 #lo40, 1041
#1048, #1049 #1056, #1057
COM 01
#lo34 #lo42 #lo50
#1058
COM 02 #1035, #1036 #lo43, #lo44 #1051, #1052
#1059, #1060
COM 03
#lo37 #lo45 #lo53
#1061
COM 04 #1038, #1039 #1046, #1047 #lo54, #lo55
#1062, #1063
173