Zenith H-100 - Address Lines; Control Lines

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DETAILED CIRCUIT DESCRIPTION
S-100 BUS INTERFACE
The S-100 Bus Interface is compatible with any IEEE
696-standard S-100 Bus. See the S-100 specification sheets
in the appendices of this manual for definitions of the
lines.
DATA IN
Data into the bus (out from the controller board) travels
through signal lines 91-95 and signal lines 41-43 on the
bus interface. These pins are used in read operations from
the status 1 atch or from the 1797 controller. The data
is buffered from the board's. internal data bus to the S-100
bus by means of U36, a 741$244 buffer.
DATA OUT
Data out from the bus (into the controller board) travels
through pins 35, 36, 38, 39, 40, 88, 89, and 90 on the bus
interface plug. This data is latched by tri-state latch
U35. The latch is used because data on the S-100 bus is
not present long enough for the 1797 to receive properly.
The tri-state latch holds the data on the board's internal
da tab us sot hat the 1797 can read it. Va 1 i d dat a is
latched in U35 on every write cycle. The latch is enabled
through pin 1 when the ALE (Address Latch Enable) signal
latches an asserted sOUT (Status Out) signal via U20.
ADDRESS LINES
The address lines from the bus enter the board through pins
29, 30, 31, 79, and 80 through 83 of the bus interface.
They are buffered by the 74LS244 chip, U34.
CONTROL LINES
The control lines from the S-100 bus enter the board through
pins 24, 25, 45. 46, and 75 through 78 of the bus inter-
face. These lines are buffered by U33.