Zenith H-100 - Interrupt Mask

3-28
INTERRUPT MASK
The interrupt mask circuits ensure that interrupt requests
are sent to the currently active CPU. The mask bit. MSK.
is set or cleared by setting or clearing bit 0 of the
processor swap port. If set. and the 8085 is active, the
8085 gets all interrupt requests. If cleared. and the 8085
is ac t i ve. the in terrupt request is blocked. However. the
swap port will disable the 8085 and enable the 8088. If
the 8088 is active. all interrupt requests are sent to the
8088 regardless of the mask bit. Here's hoW it's done .••
Immediately after reset. the 8085 CPU is the active
processor. Control lines 5SEL at U171-8 and MSK at U112-6
are logic one. These two lines connect to U225-9 and
U225-1
O. shown near the 8085 IC on the schematic. U220-2
inverts the resulting logic zero to enable U189A and U189D.
So all interrupts are sent to the 8085; maskable through
U189A. non-maskable through U189D.
The 8SEL line. which is the complement of 5SEL. disables
U1898 and U189C. the AND gates to the 8088. Later. when
the 8085 hands control to the 8088 CPU. 8SEL will go high
and 5SEL will go low.
If. while the 8085 is selected. the MSK line is set to logic
zero. U220-2 disables U189A and U189D. This blocks the
interrupt request from both the 8085 and the 8088. However.
if an interrupt request should occur. either standard or
NMI, U156-6 will go high to assert the NMINT line.
The NMINT line connects to U155-9 in the processor swap
port. The other input is the MSK line which is also high.
As a result, U155-8 goes low to assert the 8SEL line. The
H/Z-100 swaps
to the 8088 processor as described previously.
When the 8088 CPU is active. 8SEL is high to enable U1898
and U189C. U189A and U189D are disabled because 5SEL is
logic zero at U225-9. So, no matter what the setting of
the R:rK bit at U?25-10. all interrupt requests will be
routed to the BOB8 processor.