Zenith H-100 - Page 13

MAP SELECTING
Map selecting takes place at pins 1 and 15 of U111. These
two lines, MAPSELO and MAPSEL1, also go to U173-7 and -8;
but currently are not used by this IC. Depending on the
logic state of U111-1 and U111-15, plus the address on lines
BA12-BA15, the memory map will appear to be in one of the
four configurations shown in the illustration:
Confisuration 11: HAPSEL 1 = 0 HAPSELO -= 0
This is the default confisuration, memory is contiguous
from 0 to 192K.
Confisuration 12: HAPSELl =0 HAPSELO = 1
In this configuration, the first 48K of bank zero
appears to be swapped with the first 48K of bank 1-
The two 16K areas and the rest of RAH are unchanged.
This configuration may be used for HP/H while runfling
the 8085 CPU.
Configuration 13: HAPSELl = 1 HAPSELO = 0
In this configuration, the first 48K of bank zero
appears to be swapped with the first 48K of bank 2.
The two 16K areas and the middle 64K of RAH are
unchanged. This configuration alay also be used for
HP/H while running the 8085 CPU.
Confisuration 14: HAPSELl = 1 HAPSELO = 1
In this configuration, 56K in bank 0 appears to be
swapped with 5t>K in bank 1. four kilobyte buffers
above and below each 56K area remain unchanged, as
does the top 64K bank. This configuration would permit
using an extended BIOS when running CP/H-85.
3-67
Note that, in all cases, the memory only
swapped from the memory's point of view.
addresses the swapped memory, the memory map
asserts a different RAS line than it normally
appears to be
When the CPU
decoder merely
would.
10-82
For example, assume that the H/Z-100 is operating in
Configuration 114. If the CPU should write to the byte at
the 6K location, U111 would assert REN1 instead of RENO. The
memory
at the 70K location will be written to. Bear in
mind, however, that as far as the CPU (and the programmer)
is concerned, the byte at 6K was wri tten to.
Address lines BA12-BA15 allow the memory map decoder to
keep some sections of memory in place--down to 4K
increments.