Zenith H-100 - Reset Circuits

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VECTOR INTERRUPT LINES
The vector interrupt lines from the bus enter the board
at pins 4 through 11 of the bus interface. They may be
driven by U32.
READY LINE
The ready line, RDY, enters through pin 72 of the bus
interface. It is drivert by U32. The controller board uses
this line to put the CPU in a wait state during some
operations to give the controller time to finish the
operation.
RESET CIRCUITS
POWER-UP/RESET
On power up, the CPU sends RESET* through the S-100 bus
to the H-207 board . This pI aces the 1797 controller, the
control latch, the write precompensation control, and the
U26 flip-flops in a known state before the CPU accesses
the board.
In the 1797, the reset line sets the command register at
03H, the sector register to 01H, and bit 7 of the status
register (Not Ready bit) to logic zero.
After the reset line goes high, the 1797 executes the
restore command. The drive read/write head seeks track
o and sends an interrupt to the computer once the track
is found. See the 1797 IC data sheets for more details.
The reset line connects to pin 1 of the control latch, U30,
to clear all of the outputs.
The reset state of the phase lock loop control, U1, makes
the phase four (¢4) input equal to 0 (see the 1691 IC data
sheets) .
Finally, the U26 Q-outputs are made equal to 1; pin 9 sends
an RDY (ready) signal to the CPU and pin 5 provides part
·of the qualification needed for read/write enabling through
U27-11.
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