Zenith H-100 - Page 46

5-130
POWER-UP WRITE PROTECTION
On power up, the TTL circuits will be at an undefined state
until the power supply voltage rises above 4 volts. This
could generate a write command in the drives and damage
any disks that may be installed.
To protect the disk, the WG (write gate) output from the
1797 is coupled to the 5" and 8" drives through Q3 and Q2.
These transistors are biased by R25, D3-D1, and R24 to
remain cut off until the power supply voltage is at or above
4
volts. When the supply reaches this value, Q2 and Q3
are biased near their operating region and will conduct
whenever WG is asserted.
CPU/CONTROLLER LOGIC
Reading and writing in the H-207
of information: data which can
signals, and control signals.
read and control signals can only
READ STATUS LATCH (U31)
board involves three types
be read or written, status
Status signals can only be
be written.
Assume a status signal needs to be read. There are two
sources of status information for the S-100 bus, the status
port at U31 and the 1797 status register in U22.
To read from the status port, the CPU selects the H-207
by placing the address of the board on the address lines,
AO-A7. Lines A3-A7 are checked by the address comparator,
U29, for the proper address. The proper address is defined
by the user by setting DIP switch OS1. If the address is
correct, the EOUT signal pin 19 asserts.
The EOUT signal is gated through U28-13 by I/O at pin 12.
I/O asserts on a data transfer between the CPU and an I/O
port. If I/O is low, indicating that the sINP signal or
sOUT signal is asserted, then the simultaneous assertion
of EOUT and I/O signals sends a logic one to U20-2. This
logic one is latched onto pin 5 when ALE (address latch
enable) asserts. ALE, derived from pSTVAL* and pSYNC, goes
high when the H-207 port address is stable.
The Q output of U20 is NANDed with pDBIN from the S-100
bus to form RDME at U27-8. This line goes low to indicate
that the H-207 board is being read by the CPU, and activates
the status latch, U31-1.