Zenith H-100 - Page 11

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At time T4, the first positive-going edge of the 8088 clock
causes the 01 output of U188 to go high. This opens the
gate at U225A to pass the system clock, which is now the
8088 signal.
As mentioned earlier, the other function that 88SEL and
U188
perform is to ensure that the CPU being disabled is
completely disabled before the other CPU is activated.
To see how this is done, again refer to the waveforms
illustration.
Once again, assume that the H/Z-100 is switching from the
8085 to the 8088. At time T 1, the 88SEL line goes high,
which is coupled to U203-11. The other input of this
exclusive-OR gate is the Q2 line from U188. Since both
inputs are now the same state, U203-11 goes to logic zero
to preset both HOLD latches at U187.
Both CPUs respond by going into a HOLD stat~ and sending
hold-acknowledge signals to U186; the 8088 to pin 3 and
the 8085 to pin 4 through U171. This asserts HAK at pin
17 which drives the S-100 pHLDA line at U180-9.
At time T3, the Q2 line goes low and U203-11 returns to
logic one, thus releasing the latches at U187 from their
preset states. The next 88l clock pulse latches the logic
zero at U187-2 into U187-5, removing the 8088 from the hold
state.
Al so at thi s time, U 188-7 goes high to drive U215-3 high.
This last IC connects to pin 21 of the S-100 bus to form
the NDEF (8088) line. This line is a "not-to-be-defined"
line that can be used for any function by the computer
manufacturer. For the H/Z-100, this line asserts when the
8088 is active.
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