Zenith H-100 - Page 10

3-26
To see how U188 and its associated circuits block this
spike, refer to the waveforms on the previous page.
The two top waveforms are the respective clocks for the
8085 and 8088 CPUs. These are present at the inputs of
inverters U200-2 and U200-14. Assuming that the 8085 is
the active processor, then U200-1 is low and 85' couples
through the inverter to form Sl. It also couples through
U225B to clock U188.
At
time T1, the 8088 is selected; the 88SEL line goes to
logic one as shown at A on the waveforms illustration.
The next clock pulse at U188-9 latches this logic one into
U188-2, the Q1 output at B.
The next clock pulse causes the Q2 output to latch high,
shown at C. This tri-states U200 through the exclusive-DR
gate at U203B. At the same time, Q2 goes low to couple
the 88~ clock to the ~ line. Since, in this example, the
two clocks are nearly l80-degrees out of phase, the clock
immediately returns to zero, causing the spike at D in the
waveforms illustration.
Up until this time, the output of U203-8, another exclusive-
OR gate, has been logic one. This is because its inputs
Q2 and Q3 of U188 have been in opposite states. However,
since Q2 went low at time T3, both inputs to U203C are the
same, causing U203-8 to go to logic zero (waveform E).
This forces the system clock output at U225-3 to logic one
until time T4 (waveform F).