Zenith H-100 - Page 5

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TEST, Pin 23 Test Input: This input is examined
by-t"ti'e"wait-for test" software instruction. If pin
23 is low, execution continues, otherwise the processor
waits in an idle state.
MN/MX, Pin 33 Minimum/Maximum: Logic one on this
pi n pl ac es the 8088 in the minimun mode, the mode used
by the H/Z-100. When placed in the maximum mode, some
of the pin functions change. Usually, the maximlDll mode
1s used for larger systems and multi-processing systems.
RESET, Pin 21 Reset: Goes high to reset the 8088.
The interrupts are disabled, certain registers in the
8088 are set or cleared, and the instruction pointer
(program counter) points to the memory address 16 bytes
below the top end of the 1 megabyte range (FFFFOH).
This line is asserted when the RESET line at U236-11
is pull ed low. A Sc hm it t tr igger shape s this signal
and the clock circuits retimes it before applying it
to the 8088.
READY, Pin 22 Ready: This is an acknowledgement
signal from the addressed memory or I/O port that it
is ready to transfer data. When this line is low, the
CPU goes into a wait state until the addressed device
brings it high. This allows using the 8088 with slow
memory or I/O dev ices.
The READY signal is generated when U205-9 places a logic
one on U236-4. U236 synchronizes this signal with the
8088 clock to ensure correct set up and hold times.
eLK, Pin 19 8088 Clock Input. Five-megahertz clock
to provide timing to the 8088.
This signal comes from U236-8 which derives it from
the 15-MHz crystal at Y103. Duty cycle is about 33i
for optimized timing inside the 8088. When the 8088
is the active processor, this line also goes to the
processor swap port as 886 to provide system timing.
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