Acqiris SA240P - Page 20

2.1 Digitizer acquisition mode
20 Acqiris SA240P User's Manual
The effective maximum memory available for acquisition depends on several parameters, such
as the acquisition mode (single / multi-record / streaming), sampling rate, record size, number of
records, trigger delay, etc.... This maximum is determined by the driver for each specific
configuration. The AQMD3_ATTR_MAX_SAMPLES_PER_CHANNEL attribute in IVI-C or
IAqMD3Acquisition.MaxSamplesPerChannel property in IVI.NET can be used to retrieve
the maximum number of samples per channel that can be acquired for a specific configuration.
When using the Soft Front Panel, the Max Samples per channel parameter is given on the
Acquisition panel.
Acquisition time (Timebase range)
The timebase range defines the time period over which data is being acquired.
For example, the SA240P has a standard acquisition memory of 4 GB, i.e. 1 GSample/ch and a
sampling rate of 4 GS/s. Therefore, at the maximum sampling rate, the ADC card can record a
signal over a time window of up to 250 ms/ch.
Model
Memory option
ordered
Acquisition
memory
Max sampling rate
Max recording time
window at higher
sampling rate
SA240
-MEA (default) 4 GB
4 GS/s
250 ms on 2 channels
500 ms on 1 channel
-MEB (optional) 8 GB
500 ms on 2 channels
1 s on 1 channel
Table 2.2 - Maximum recorded time at maximum sampling rate, depending on ordered memory option.
Maximum acquisition time
There is a limit on the acquisition time / acquisition length in digitizer mode depending on the record
size, post trigger delay and binary decimation factor. Above this limit, the driver returns a post-trigger
overflow.
Acquired data format
The raw 14-bit data is subjected to post-calibration processing, which compensates for gain and
offset errors in the internal ADCs, The result of this post-processing is then stored and read-out as a
16-bit value. For this reason the returned data will not always be divisible by 4 as may be expected,
neither equally spaced.
Signed left-aligned 16-bit ADC code
The signed, raw ADC code is shifted to the left to align to 16 bits. The result is then converted, with
the sign, to the final format (16, 32 or 64 bits).
For the 14-bit SA240P, signed left-aligned 16-bit ADC code means that the signed raw ADC code is
shifted to the left by 2 bits, and coded in 2’s complement to the final number of bits (16, 32 or 64) as
illustrated below.