Akai AP-D40

2.
MODEL
AP-Q60/C
(Refer
to
the
schematic
diagram.)
Fe
SS
SS
SS
SS
SS
ye
7
|
@5)
TP2
I
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xf
osc
72
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|
@6)
FG
IN
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|
j
(4)
33
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|
(5)
45
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STR
OBO
(7)
(6)
33/45
OUT
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|
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$i
(9)
|
$2(0)
{
$3q)
|
$42
|
1
|
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TPI@3)
|
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LOCK
|
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|
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|
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ves-P
C1)
SAMPLE
SAMPLE
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&
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ve6-IP
(8)
HOLD
HOLD
@4)Vec
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L_@--©--
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Vss VGG
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APC
OUT
P-Ci
P-C2
F-Cr
F-C2
AFC
OUT
Fig.
12
The
AP-Q60
has
a
photo
sensor
which
picks
up
the
FG
signal
from
the
stroboscope
pattern
on
the
underside
of
the
platter
in
order
to
detect
the
speed.
The
servo
circuit
also
employs
PLL
LSI
AP400A
for
motor
control
and
it
is
a
quartz
lock
system.
AP-400A
is
an
N
channel
silicon
gate
MOS
type
LSI
which
has
been
developed
for
speed
control
of
quartz
lock
DD
motors.
In
Fig.
12’s
block
diagram
and
Chart
1,
the
relation-
ship
between
the
terminal
signal
and
operation
mode
is
shown.
AP-400A
outputs
voltage
proportionate
to
the
number
of
revolutions
(AFC-OUT),
and
voltage
proportionate
to
the
phase
(APC-OUT).
The
FG
signal
input
from
the
FG
sensor
enters
the
base
of
TR2,
is
rectified
and
then
enters
AP-400A’s
FG
IN
terminal.
Next
there
is
a
5.4
MHz
oscillation
by
C1
and
the
X’tal
(5.4
MHz)
which
is
scaled
down
to
1/2
by
the
T-Flip
Flop.
This
scaled
down
signal
of
2.7MHz
is
the
standard
frequency
and
is
input
into
AP-400A’s
XT
terminal.
A
voltage
proportionate
to
the
number
of
revolutions
is
put
out
from
AFC-OUT
and
another
voltage
pro-
portionate
to
the
phase
appears
in
APC-OUT
due
to
AP-400A.
When
the
quartz
lock
is
on,
these
AFC-
OUT
and
APC-OUT
voltages
are
compared
and
amplified.
Next
they
pass
a
low
pass
filter
and
are
made
into
a
DC
control
signal
of
the
TR6’s
base
bias.
As
a
result,
the
collector
current
flows
and
the
Hall
element
current
is
controlled.
When
the
quartz
lock
is
off,
a
standard
voltage
from
R26
and
R27
and
the
AFC-OUT
voltage
are
com-
pared
and
amplified
and
the
Hall
element
current
is
controlled.
Pitch
control
controls
the
speed,
changing
the
AFC-OUT
voltage
by
changing
the
VGG-F
addition
voltage.
i
ee
ec
eae
Sa
16