Alcatel-Lucent 7450 ESS-12 - Figure 12: Peer Clocks

Page 232 7450 ESS OS Basic System Configuration Guide
Figure 9: Synchronization Reference Selection
The recovered clock will be able to derive its timing from any of the following:
• OC3/STM1, OC12/STM4, OC48/STM16, OC192/STM64 ports
• Synchronous Ethernet ports
•
• BITS port on the CPM or CFM module
• IEEE 1588v2 slave port (PTP)
OSSG326
Qualifier
T1/E1,
SONET/SDH,
SyncE,
ACR
Internal
(Node)
Timing
Reference
T1/E1
Quality
Level (QL)
Mode 1)
Priority
Reference Order
Mode 2) QL Then
Priority Reference
Order
BITS - Out
Digital Phase
Locked Loop
(DPLL)
Quality Level
Override
Reference
Selector
Quality
Level (QL)
Quality
Level (QL)
Qualifier
Qualifier
BITSIn
Ref 2
Ref 1
T1/E1
Qualifier
BITSIn
Quality
Level (QL)
OSSG731
Qualifier
T1/E1,
SONET/SDH
SyncE, ACR
Internal
(Node)
Timing
Reference
T1/E1
Quality
Level (QL)
Mode 1)
Priority
Reference Order
Mode 2) QL Then
Priority Reference
Order
BITS
Output
Selector
Digital Phase
Locked Loop
(DPLL)
Quality Level
Override
Reference
Selector
Quality
Level (QL)
Quality
Level (QL)
Qualifier
Qualifier
BITSIn
2
Ref 2
Ref 1
BITSout
Quality
Level (QL)
Quality
Level (QL)
T1/E1 Qualifier
BITSIn
1
1588 Qualifier
PTP