System Management
7450 ESS OS Basic System Configuration Guide Page 233
All settings of the signal characteristics for the BITS input applies to both ports. When the active
CPM considers the BITS input as a possible reference, it will consider first the BITS input port on
the active CPM followed the BITS input port on the standby CPM in that relative priority order.
This relative priority order is in addition to the user definable ref-order. For example, a ref-order
of ‘bits-ref1-ref2’ would actually be BITS in (active CPM) followed by BITS in (standby CPM)
followed by ref1 followed by ref2. When ql-selection is enabled, then the QL of each BITS input
port shall be viewed independently. The higher QL source shall be chosen.
The BITS output ports can be configured to provided either the an unfiltered recovered line clock
from a SR/ESS port or the output of the central clock of the 7750 SR. The first case would be used
if the port was connected to deliver an input reference directly to dedicated timing device in the
facility (BITS or SASE device). The second case would be used to test the quality of the clocking
used by the 7750 SR.
When QL selection mode is disabled, then the reversion setting controls when the central clock
can re-select a previously failed reference.
The Table 23 shows the selection followed for two reference in both revertive and non-revertive
modes:
Table 22: Revertive, non-Revertive Timing Reference Switching Operation
Status of
Reference A
Status of
Reference B
Active Reference
Non-revertive Case
Active Reference
Revertive Case
OK OK A A
Failed OK B B
OK OK B A
OK Failed A A
OK OK A A
Failed Failed holdover holdover
OK Failed A A
Failed Failed holdover holdover
Failed OK B B
Failed Failed holdover holdover
OK OK A or B A
To Next Page
Loading...
