Altera Cyclone V - Page 48

2–40 Chapter 2: Board Components
Memory
Cyclone V GT FPGA Development Board August 2017 Altera Corporation
Reference Manual
C7 DDR3A_DQS_P1 AD19
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 1
B7
DDR3A_DQS_N1 AE19
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 1
K1
DDR3A_ODT AN21 1.5-V SSTL Class I On-die termination enable
J3
DDR3A_RASN AP14 1.5-V SSTL Class I Row address select
T2
DDR3A_RESETN AJ22 1.5-V SSTL Class I Reset
L3
DDR3A_WEN AN12 1.5-V SSTL Class I Write enable
L8
DDR3A_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U27)
N3
DDR3A_A0 AK18 1.5-V SSTL Class I Address bus
P7
DDR3A_A1 AL18 1.5-V SSTL Class I Address bus
P3
DDR3A_A2 AM18 1.5-V SSTL Class I Address bus
N2
DDR3A_A3 AN18 1.5-V SSTL Class I Address bus
P8
DDR3A_A4 AH17 1.5-V SSTL Class I Address bus
P2
DDR3A_A5 AJ17 1.5-V SSTL Class I Address bus
R8
DDR3A_A6 AK17 1.5-V SSTL Class I Address bus
R2
DDR3A_A7 AL17 1.5-V SSTL Class I Address bus
T8
DDR3A_A8 AH16 1.5-V SSTL Class I Address bus
R3
DDR3A_A9 AJ16 1.5-V SSTL Class I Address bus
L7
DDR3A_A10 AL16 1.5-V SSTL Class I Address bus
R7
DDR3A_A11 AM16 1.5-V SSTL Class I Address bus
N7
DDR3A_A12 AM13 1.5-V SSTL Class I Address bus
T3
DDR3A_A13 AN13 1.5-V SSTL Class I Address bus
M2
DDR3A_BA0 AN16 1.5-V SSTL Class I Bank address bus
N8
DDR3A_BA1 AN17 1.5-V SSTL Class I Bank address bus
M3
DDR3A_BA2 AP17 1.5-V SSTL Class I Bank address bus
K3
DDR3A_CASN AP15 1.5-V SSTL Class I Row address select
K9
DDR3A_CKE AP26 1.5-V SSTL Class I Column address select
J7
DDR3A_CLK_P AA18
Differential 1.5-V SSTL
Class I
Differential output clock
K7
DDR3A_CLK_N AA17
Differential 1.5-V SSTL
Class I
Differential output clock
L2
DDR3A_CSN AA16 1.5-V SSTL Class I Chip select
E7
DDR3A_DM2 AM28 1.5-V SSTL Class I Write mask byte lane
D3
DDR3A_DM3 AL27 1.5-V SSTL Class I Write mask byte lane
E3
DDR3A_DQ16 AP27 1.5-V SSTL Class I Data bus byte lane 2
F7
DDR3A_DQ17 AN27 1.5-V SSTL Class I Data bus byte lane 2
F2
DDR3A_DQ18 AK22 1.5-V SSTL Class I Data bus byte lane 2
Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board Reference
Schematic
Signal Name
Cyclone V GT
Pin Number
I/O Standard Description
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