Altera DE1 - Page 44

DE1 User Manual
42
Figure 4.25. Flash schematic.
Signal Name FPGA Pin No.
Description
DRAM_ADDR[0]
PIN_W4 SDRAM Address[0]
DRAM_ADDR[1]
PIN_W5 SDRAM Address[1]
DRAM_ADDR[2]
PIN_Y3 SDRAM Address[2]
DRAM_ADDR[3]
PIN_Y4 SDRAM Address[3]
DRAM_ADDR[4]
PIN_R6 SDRAM Address[4]
DRAM_ADDR[5]
PIN_R5 SDRAM Address[5]
DRAM_ADDR[6]
PIN_P6 SDRAM Address[6]
DRAM_ADDR[7]
PIN_P5 SDRAM Address[7]
DRAM_ADDR[8]
PIN_P3 SDRAM Address[8]
DRAM_ADDR[9]
PIN_N4 SDRAM Address[9]
DRAM_ADDR[10]
PIN_W3 SDRAM Address[10]
DRAM_ADDR[11]
PIN_N6 SDRAM Address[11]
DRAM_DQ[0] PIN_U1 SDRAM Data[0]
DRAM_DQ[1] PIN_U2 SDRAM Data[1]
DRAM_DQ[2] PIN_V1 SDRAM Data[2]
DRAM_DQ[3] PIN_V2 SDRAM Data[3]
DRAM_DQ[4] PIN_W1 SDRAM Data[4]
DRAM_DQ[5] PIN_W2 SDRAM Data[5]
DRAM_DQ[6] PIN_Y1 SDRAM Data[6]