Altera DE1 - Page 45

DE1 User Manual
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DRAM_DQ[7] PIN_Y2 SDRAM Data[7]
DRAM_DQ[8] PIN_N1 SDRAM Data[8]
DRAM_DQ[9] PIN_N2 SDRAM Data[9]
DRAM_DQ[10] PIN_P1 SDRAM Data[10]
DRAM_DQ[11] PIN_P2 SDRAM Data[11]
DRAM_DQ[12] PIN_R1 SDRAM Data[12]
DRAM_DQ[13] PIN_R2 SDRAM Data[13]
DRAM_DQ[14] PIN_T1 SDRAM Data[14]
DRAM_DQ[15] PIN_T2 SDRAM Data[15]
DRAM_BA_0 PIN_U3 SDRAM Bank Address[0]
DRAM_BA_1 PIN_V4 SDRAM Bank Address[1]
DRAM_LDQM PIN_R7 SDRAM Low-byte Data Mask
DRAM_UDQM PIN_M5 SDRAM High-byte Data Mask
DRAM_RAS_N PIN_T5 SDRAM Row Address Strobe
DRAM_CAS_N PIN_T3 SDRAM Column Address Strobe
DRAM_CKE PIN_N3 SDRAM Clock Enable
DRAM_CLK PIN_U4 SDRAM Clock
DRAM_WE_N PIN_R8 SDRAM Write Enable
DRAM_CS_N PIN_T6 SDRAM Chip Select
Table 4.16. SDRAM pin assignments.
Signal Name FPGA Pin No.
Description
SRAM_ADDR[0]
PIN_AA3 SRAM Address[0]
SRAM_ADDR[1]
PIN_AB3 SRAM Address[1]
SRAM_ADDR[2]
PIN_AA4 SRAM Address[2]
SRAM_ADDR[3]
PIN_AB4 SRAM Address[3]
SRAM_ADDR[4]
PIN_AA5 SRAM Address[4]
SRAM_ADDR[5]
PIN_AB10 SRAM Address[5]
SRAM_ADDR[6]
PIN_AA11 SRAM Address[6]
SRAM_ADDR[7]
PIN_AB11 SRAM Address[7]
SRAM_ADDR[8]
PIN_V11 SRAM Address[8]
SRAM_ADDR[9]
PIN_W11 SRAM Address[9]
SRAM_ADDR[10]
PIN_R11 SRAM Address[10]
SRAM_ADDR[11]
PIN_T11 SRAM Address[11]
SRAM_ADDR[12]
PIN_Y10 SRAM Address[12]
SRAM_ADDR[13]
PIN_U10 SRAM Address[13]