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General| Brand | Altera |
|---|---|
| Model | Stratix |
| Category | Motherboard |
| Language | English |
Introduces PLLs, their types (enhanced and fast), and features for clock management.
Details TriMatrix memory structures, sizes (M512, M4K, M-RAM), configurations, and features.
Covers external memory standards like DDR SDRAM, RLDRAM II, QDR SRAM, and ZBT SRAM.
Discusses various industry I/O standards and guidelines for their use in Stratix/Stratix GX devices.
Details Stratix high-speed differential I/O capabilities, SERDES, and related standards.
Provides guidelines for programmable I/O standards and essential information for system design.
Information for design and optimization of DSP functions and arithmetic operations in on-chip DSP blocks.
Describes implementation of high-performance DSP functions using Stratix/Stratix GX DSP blocks.
Details the two columns of DSP blocks in Stratix/Stratix GX devices, configurable for multipliers.
Lists the elements of the DSP block: multiplier, adder/subtractor/accumulator, summation, etc.
Describes implementing basic FIR filters using dedicated DSP blocks with integrated multipliers and adders.
Details TDM FIR filter implementation using multiplier-adder mode and shift registers.
Describes implementing polyphase interpolation filters using Stratix/Stratix GX DSP blocks and multiplexers.
Discusses polyphase implementation of decimation filters to reduce computational requirements.
Explains implementation of complex FIR filters using two-multiplier adder mode in DSP blocks.
Describes basic IIR filter implementation using cascaded second order blocks or biquads.
Explains implementing basic IIR filters using multiplier blocks, adders, and delay elements in DSP blocks.
Discusses DSP's reliance on matrix manipulation for transforming digital signals.
Summarizes Stratix/Stratix GX devices extending APEX features for SOPC solutions and enhancing design flexibility.
Discusses IP functions offered by Altera for Stratix devices, focusing on 10-Gigabit Ethernet.
Provides documentation on IP functions for Stratix/Stratix GX devices, focusing on SFI-4 interface.
Highlights new features and architectural enhancements in Stratix/Stratix GX devices over APEX II/20K.
Describes TriMatrix memory with three different block sizes (M512, M4K, M-RAM) and features.
Describes Stratix/Stratix GX DSP blocks outperforming LE-based implementations, with configurable multipliers.
Highlights Stratix/Stratix GX PLL enhancements over APEX II/APEX 20K PLLs, including new features.
Discusses support for high-speed differential interfaces up to 840 Mbps using fast PLLs and SERDES.
Provides configuration and remote system upgrade information for Stratix devices.
Discusses remote system configuration and interfacing with enhanced configuration devices.
Describes how FPGAs store configuration data in SRAM cells and the device states during operation.
Discusses parallel configuration for faster configuration times and byte-wide data transfer.
Explains the three major parts of remote system configuration: data reception, storage, and device updating.
Provides package information for Altera Stratix devices, including cross reference and package outlines.
Provides guidelines for designing with Stratix/Cyclone devices using 1.5-V operating voltage.
Introduces Cyclone FPGA family for high-volume, cost-sensitive applications using 1.5-V operating voltage.
Explains generating 1.5-V supply using voltage regulators and their importance for low-power applications.
Provides a checklist to help select the proper regulator based on design requirements and parameters.
Shows process for selecting voltage regulators for Cyclone devices based on power consumption.
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