Altera Stratix - V Differential HSTL - EIA;JEDEC Standard EIA;JESD8-6; V PCI Local Bus - PCI Special Interest Group PCI Local Bus Specification Rev. 2.3

4–6 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data
rate (QDR) memory clock interfaces. The differential HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V ≤V
I
≤V
CCIO
+ 0.3 V. Differential HSTL
does not require an input reference voltage, however, it does require a
50 Ω resistor termination resistor to V
TT
at the input buffer (see
Figure 4–3). Stratix and Stratix GX devices support both input and output
clock levels for 1.5-V differential HSTL. The input clock is implemented
using dedicated differential input buffer. Two single-ended output
buffers are automatically programmed to have opposite polarity so as to
implement a differential output clock.
Figure 4–3. 1.5-V Differential HSTL Class I Termination
3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus
Specification Rev. 2.3
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification revision 2.3 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires 3.3-V V
CCIO
. Stratix and Stratix GX devices are fully compliant
with the 3.3-V PCI Local Bus Specification Revision 2.3 and meet
64-bit/66-MHz operating frequency and timing requirements. The 3.3-V
PCI standard does not require input reference voltages or board
terminations. Stratix and Stratix GX devices support both input and
output levels.
Differential
Transmitter
Differential
Receiver
Z
0
= 50 Ω
50 Ω 50 Ω
Z
0
= 50 Ω
V
TT
= 0.75 V V
TT
= 0.75 V