Altera Corporation 11–41
July 2005 Stratix Device Handbook, Volume 2
Configuring Stratix & Stratix GX Devices
The Quartus II software verifies successful JTAG configuration upon
completion. The software checks the state of CONF_DONE through the
JTAG port. If CONF_DONE is not in the correct state, the Quartus II
software indicates that configuration has failed. If CONF_DONE is in the
correct state, the software indicates that configuration was successful.
1 If VCCIO is tied to 3.3 V, both the I/O pins and JTAG TDO port
drive at 3.3-V levels.
Do not attempt JTAG and non-JTAG configuration simultaneously. When
configuring through JTAG, allow any non-JTAG configuration to
complete first.
Figure 11–22 shows the JTAG configuration of a Stratix or Stratix GX
device with a microprocessor.
Figure 11–22. JTAG Configuration of Stratix & Stratix GX Devices with a
Microprocessor
Notes to Figure 11–22:
(1) Connect the nCONFIG, MSEL2, MSEL1, and MSEL0 pins to support a non-JTAG
configuration scheme. If your design only uses JTAG configuration, connect the
nCONFIG pin to V
CC
and the MSEL2, MSEL1, and MSEL0 pins to ground.
(2) Pull DATA0 and DCLK to either high or low.
Configuration with JRunner Software Driver
JRunner is a software driver that allows you to configure Altera FPGAs
through the ByteBlasterMV download cable in JTAG mode. The
programming input file supported is in Raw Binary File (.rbf) format.
JRunner also requires a Chain Description File (.cdf) generated by the
Quartus II software. JRunner is targeted for embedded JTAG
configuration. The source code has been developed for the Windows NT
operating system. You can customize the code to make it run on other
platforms.
nCONFIG
DATA0
DCLK
TDI
TCK
TMS
Microprocessor
Memory
ADDR
DATA
TDO
Stratix or
Stratix GX Device
nSTATUS
CONF_DONE
V
CC
V
CC
10 kΩ
10 kΩ
(2)
(1)
(2)
(1)
(1)
(1)
MSEL2
MSEL1
MSEL0
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