3–20 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
DDR Memory Support Overview
DDR Registers
Each Stratix and Stratix GX IOE contains six registers and one latch. Two
registers and a latch are used for input, two registers are used for output,
and two registers are used for output enable control. The second output
enable register provides the write preamble for the DQS strobe in the
DDR external memory interfaces. This negative-edge output enable
register extends the high-impedance state of the pin by a half clock cycle
to provide the external memory's DQS preamble time specification.
Figure 3–10 shows the six registers and the latch in the Stratix and
Stratix GX IOE and Figure 3–11 shows how the second OE register
extends the DQS high impedance state by half a clock cycle during a write
operation.
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