Altera Stratix - Lvpecl; Pseudo Current Mode Logic (PCML)

Altera Corporation 4–13
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
f For more information on the LVDS I/O standard in Stratix devices, see
the High-Speed Differential I/O Interfaces in Stratix Devices chapter.
LVPECL
The LVPECL I/O standard is a differential interface standard requiring a
3.3-V V
CCIO.
The standard is used in applications involving video
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. The LVPECL
standard does not require an input reference voltage, but it does require
a 100-Ω termination resistor between the two signals at the input buffer.
See Figures 4–14 and 4–15 for two alternate termination schemes for
LVPECL. Stratix and Stratix GX devices support both input and output
levels.
Figure 4–14. LVPECL DC Coupled Termination
Figure 4–15. LVPECL AC Coupled Termination
Pseudo Current Mode Logic (PCML)
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applications such as networking and
telecommunications. The standard requires a 3.3-V V
CCIO
. The PCML I/O
standard consumes less power than the LVPECL I/O standard. The
Output Buffer Input Buffer
100 Ω
Z = 50 Ω
Z = 50 Ω
Output Buffer
Input Buffe
r
100 Ω
Z = 50 Ω
Z = 50 Ω
V
CCIO
V
CCIO
R2 R2
R1 R1
10 to 100 nF
10 to 100 nF