Altera Stratix - Mixing Voltage Referenced & Non-Voltage Referenced Standards

Altera Corporation 4–25
June 2006 Stratix Device Handbook, Volume 2
Selectable I/O Standards in Stratix & Stratix GX Devices
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards
use the same V
REF
setting. For example, although one I/O bank can
implement both SSTL-3 and SSTL-2 I/O standards, I/O pins using these
standards must be in different banks since they require different V
REF
values
For voltage-referenced inputs, the receiver compares the input voltage to
the voltage reference and does not take into account the V
CCIO
setting.
Therefore, the V
CCIO
setting is irrelevant for voltage referenced inputs.
Voltage-referenced bidirectional and output signals must be the same as
the I/O bank’s V
CCIO
voltage. For example, although you can place an
SSTL-2 input pin in any I/O bank with a 1.25-V V
REF
level, you can only
place SSTL-2 output pins in an I/O bank with a 2.5-V V
CCIO
.
Mixing Voltage Referenced & Non-Voltage Referenced
Standards
Non-voltage referenced and voltage referenced pins can safely be mixed
in a bank by applying each of the rule-sets individually. For example, on
I/O bank can support SSTL-3 inputs and 1.8-V LVCMOS inputs and
outputs with a 1.8-V V
CCIO
and a 1.5-V V
REF
. Similarly, an I/O bank can
support 1.5-V LVCMOS, 3.3-V LVTTL (inputs, but not outputs), and
HSTL I/O standards with a 1.5-V V
CCIO
and 0.75-V V
REF
.
For the voltage-referenced examples, see the “I/O Pad Placement
Guidelines” section. For details on how the Quartus II software supports
I/O standards, see the “Quartus II Software Support”section.