Altera Stratix - I;O Characteristics for XSBI, XGMII & XAUI; Software Implementation; AC;DC Specifications

8–22 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
I/O Characteristics for XSBI, XGMII & XAUI
Software Implementation
You can use the Assignment Organizer in the Altera
®
Quartus
®
II
software to implement the I/O standards for a particular interface. For
example, set the I/O standard to LVDS for XSBI and to HSTL Class I for
XGMII. You can use the MegaWizard
®
Plug-In Manager to create the
PLLs and transmitter and receiver SERDES blocks for the XSBI
implementation and PLLs and DDR input and output circuitry for the
XGMII implementation. For more information on the Assignment
Organizer or MegaWizard Plug-In Manager, see the Quartus II Software
Help.
AC/DC Specifications
Table 8–10 lists the XSBI DC electrical characteristics, similar to Stratix
and Stratix GX devices, that are based on the ANSI/TIA-644 LVDS
specification.
I/O characteristics for the 1.5-V HSTL standard for Stratix and Stratix GX
devices are shown in Figure 8–17 and comply with XGMII electrical
specifications available in 10-Gigabit Ethernet draft IEEE P802.3ae.
Table 8–10. XSBI DC Specifications
Parameter
Value
Unit
Min Typ Max
Output differential voltage (V
OD
) 250 400 (1) mV
Output offset voltage (V
OS
) 1,125 1,375 mV
Output Impedance, single ended 40 140 W
Change in V
OD
between ‘0’ and ‘1’ 50 mV
Change in V
OS
between ‘0’ and ‘1’ 50 mV
Input voltage range (V
I
) 900 1,600 mV
Differential impedance 100 W
Input differential voltage (V
ID
) 100 600 mV
Receiver differential input impedance 70 130 W
Ground potential difference (between PCS and PMA) 50 mV
Rise and fall times (20% to 80%) 100 400 ps
Note to Table 8–10:
(1) Larger V
OD
is possible for better signal intensity.