Altera Stratix - Section V. IP & Design Considerations; Chapter 8. Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices; Chapter 9. Implementing SFI-4 in Stratix & Stratix GX Devices; Chapter 10. Transitioning APEX Designs to Stratix & Stratix GX Devices

Altera Corporation Section V–1
Section V. IP & Design
Considerations
This section provides documentation on some of the IP functions offered
by Altera
®
for Stratix
®
devices. (Also see the Intellectual Property section
of the Altera web site for a complete offering of IP cores for Stratix
devices.) The last chapter details design considerations for migrating
from the APEX
™
architecture.
This section contains the following chapters:
■ Chapter 8, Implementing 10-Gigabit Ethernet Using Stratix &
Stratix GX Devices
■ Chapter 9, Implementing SFI-4 in Stratix & Stratix GX Devices
■ Chapter 10, Transitioning APEX Designs to Stratix & Stratix GX
Devices
Revision History
The table below shows the revision history for Chapters 8 through 10.
Chapter Date/Version Changes Made
8 July 2005, v2.0 Updated Stratix GX device information.
September 2004, v1.2
● Table 8–2 on page 8–10: updated table, deleted Note 1, and updated
Note 2.
● Updated Table 8–4 on page 8–12.
November 2003, v1.1
● Removed support for series and parallel on-chip termination.
April 2003, v1.0
● No new changes in Stratix Device Handbook v2.0.
9 July 2005, v2.0
● Updated Stratix GX device information.
September 2004, v1.1
● Table 9–2 on page 9–9: updated table, deleted Note 1, and updated
Note 2.
● Updated Table 9–4 on page 9–10.
April 2003, v1.0
● No new changes in Stratix Device Handbook v2.0.