Altera Stratix - Summary

Altera Corporation 5–75
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–48. SERDES Bypass LVDS Transmitter with Logic Array as Deserializer
Summary
The Stratix device family of flexible, high-performance, high-density
PLDs delivers the performance and bandwidth necessary for complex
system-on-a-programmable-chip (SOPC) solutions. Stratix devices
support multiple I/O protocols to interface with other devices within the
system. Stratix devices can easily implement processing-intensive data-
path functions that are received and transmitted at high speeds. The
Stratix family of devices combines a high-performance enhanced PLD
architecture with dedicated I/O circuitry in order to provide I/O
standard performances of up to 840 Mbps.
PLL
Counter
Shift
Register
Shift
Register
DDR
Output
Clock
×1 clock
×4 clock
data_h
data_l
Data[7..0]
clock
clock
data
data
load
load
Serial
data out
tx_clk