Altera Stratix - Mixed-Port Read-During-Write Mode

Altera Corporation 10–11
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
Figure 10–5. Rising Edge Feed-Through Behavior
(Stratix & Stratix GX Devices) Note (1)
Note to Figure 10–5:
(1) Figures 10–4 and 10–5 assume that the address stays constant throughout and that
the outputs are not registered.
Mixed-Port Read-During-Write Mode
Mixed-port read-during-write mode occurs when a RAM block in simple
or true dual-port mode has one port reading and the other port writing to
the same address location using the same clock. In APEX II and
APEX 20K designs, the ESB outputs the old data in the first half of the
clock cycle and the new data in the second half of the clock cycle, as
indicated by Figure 10–6.
Figure 10–6. Mixed-Port Feed-Through Behavior
(APEX II & APEX 20K Devices) Note (1)
Note to Figure 10–6:
(1) Figure 10–6 assumes that outputs are not registered.
Stratix and Stratix GX device RAM outputs the new data on the rising
edge of the clock cycle immediately after the data was written. When you
use Stratix and Stratix GX M512 and M4K blocks, you can choose whether
to output the old data at the targeted address or output a don’t care value
during the clock cycle when the new data is written. M-RAM blocks
inclock
data_in
wren
data_out
A
BA
Old
inclock
Port A
data_in
Port A
wren
Port B
data_out
A
B
A
Old
Port B
wren
B