Altera Stratix - Fast PLL SERDES Channel Support

Altera Corporation 5–23
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Fast PLL SERDES Channel Support
The Quartus II MegaWizard Plug-In Manager only allows you to
implement up to 20 receiver or 20 transmitter channels for each fast PLL.
These channels operate at up to 840 Mbps. For more information on
implementing more than 20 channels, see “Fast PLLs” on page 5–52. The
receiver and transmitter channels are interleaved such that each I/O bank
on the left and right side of the device has one receiver channel and one
transmitter channel per row. Figure 5–16 shows the fast PLL and channel
layout in EP1S10, EP1S20, and EP1S25 devices. Figure 5–17 shows the fast
PLL and channel layout in EP1S30 to EP1S80 devices.
f For more the number of channels in each device, see Tables 5–10 through
5–14.
Figure 5–16. Fast PLL & Channel Layout in EP1S10, EP1S20 & EP1S25 Devices Note (1)
Notes to Figure 5–16:
(1) Wire-bond packages only support up to 624 Mbps until characterization shows otherwise.
(2) See Tables 5–10 through 5–14 for the exact number of channels each package and device density supports.
(3) There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Fast
PLL 1
Fast
PLL 2
(3)
Fast
PLL 4
Fast
PLL 3
(3)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)