Altera Stratix - SERDES Bypass Mode

5–70 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
separate the transmitter and receiver in your design, the Quartus II
software merges the fast PLLs when appropriate and gives you the
following message:
Receiver fast PLL <lvds_rx pll name> and transmitter fast PLL
<lvds_tx pll name> are merged together
The Quartus II software gives the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
Can't merge transmitter-only fast PLL
<lvds_tx pll name> and receiver-only fast PLL
<lvds_rx pll name>
tx_outclock Resource
You can use either the global or regional clock for the tx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
SERDES Bypass Mode
You can bypass the SERDES block if your data rate is less than 624 Mbps,
and you must bypass the SERDES block for the ×1 and ×2 LVDS modules.
Since you cannot route the fast PLL output to an output pin, you must
create additional DDR I/O circuitry for the transmitter clock output. To
create an ×J transmitter output clock, instantiate an alt_ddio
megafunction clocked by the
×J clock with datain_h connected to V
CC
and datain_l connected to GND.
×1 Mode
For ×1 mode, you only need to specify the I/O standard of the pins to tell
the Quartus II software that you are using differential signaling.
However, Altera recommends using the DDRIO circuitry when the input
or output data rate is higher than 231 Mbps. The maximum output clock
frequency for ×1 mode is 420 MHz.
×2 Mode
You must use the DDRIO circuitry for ×2 mode. The Quartus II software
provides the altddio_in and altddio_out megafunctions to use for
×2 receiver and ×2 transmitter, respectively. The maximum data rate in
×2 mode is 624 Mbps. Figure 5–44 shows the schematic for using DDR
circuitry in
×2 mode.