11–42 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Configuration Schemes
f For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and zip file.
Jam STAPL Programming & Test Language
The Jam
TM
Standard Test and Programming Language (STAPL), JEDEC
standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or
configuration of programmable devices and testing of electronic systems,
using the IEEE 1149.1 JTAG interface. Jam STAPL is a freely licensed open
standard.
Connecting the JTAG Chain to the Embedded Processor
There are two ways to connect the JTAG chain to the embedded processor.
The most straightforward method is to connect the embedded processor
directly to the JTAG chain. In this method, four of the processor pins are
dedicated to the JTAG interface, saving board space but reducing the
number of available embedded processor pins.
Figure 11–23 illustrates the second method, which is to connect the JTAG
chain to an existing bus through an interface PLD. In this method, the
JTAG chain becomes an address on the existing bus. The processor then
reads from or writes to the address representing the JTAG chain.
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