Altera Stratix - SSTL-2 Class I & II - EIA;JEDEC Standard JESD8-9 A

4–10 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
Stratix & Stratix GX I/O Standards
Figure 4–7. SSTL-3 Class I Termination
Figure 4–8. SSTL-3 Class II Termination
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
operation in conditions where a bus must be isolated from large stubs.
The SSTL-2 standard specifies an input voltage range of
–0.3V≤V
I
≤V
CCIO
+ 0.3 V. SSTL-2 requires a 1.25-V V
REF
and a 1.25-V
V
TT
to which the series and termination resistors are connected (see
Figures 4–9 and 4–10). Stratix and Stratix GX devices support both input
and output levels.
Figure 4–9. SSTL-2 Class I Termination
Output Buffer
Input Buffer
V
TT
= 1.5 V
50 Ω
25 Ω
Z = 50 Ω
V
REF
= 1.5 V
Output Buffer
Input Buffer
V
TT
= 1.5 V
50 Ω
V
TT
= 1.5 V
50 Ω
25 Ω
Z = 50 Ω
V
REF
= 1.5 V
Output Buffer
Input Buffer
V
TT
= 1.25 V
50 Ω
25 Ω
Z = 50 Ω
V
REF
= 1.25 V