5–16 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Differential I/O Interface & Fast PLLs
Differential I/O
Interface & Fast
PLLs
Stratix devices provide 16 dedicated global clocks, 8 dedicated fast
regional I/O pins, and up to 16 regional clocks (four per device quadrant)
that are fed from the dedicated global clock pins or PLL outputs. The 16
dedicated global clocks are driven either by global clock input pins that
support all I/O standards or from enhanced and fast PLL outputs.
Stratix devices use the fast PLLs to implement clock multiplication and
division to support the SERDES circuitry. The input clock is either
multiplied by the W feedback factor and/or divided by the J factor. The
resulting clocks are distributed to SERDES, local, or global clock lines.
Fast PLLs are placed in the center of the left and right sides for EP1S10 to
EP1S25 devices. For EP1S30 to EP1S80 devices, fast PLLs are placed in the
center of the left and right sides, as well as the device corners (see
Figure 5–13). These fast PLLs drive a dedicated clock network to the
SERDES in the rows above and below or top and bottom of the device as
shown in Figure 5–13.
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