Altera Stratix - Page 197

Altera Corporation 5–17
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–13. Stratix Fast PLL Positions & Clock Naming Convention Note (1)
Notes to Figure 5–13:
(1) Dedicated clock input pins on the right and left sides do not support PCI or PCI-X 1.0.
(2) PLLs 7, 8, 9, and 10 are not available on the EP1S30 device in the 780-pin FineLine BGA
®
package.
FPLLCLK0 FPLLCLK3
FPLLCLK2
CLK[11..8]
FPLLCLK1
CLK[3..0]
7
1
2
8
10
4
3
9
115
126
CLK[7..4]
CLK[15..12]
PLLs