Altera Stratix - Clock Output Connections

Altera Corporation 1–43
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Clock Output Connections
Enhanced PLLs have outputs for two regional clock outputs and four
global outputs. There is line sharing between clock pins, global and
regional clock networks and all PLL outputs. Check Tables 1–15 and 1–16
and Figures 1–21 and 1–22 to make sure that the clocking scheme is valid.
The Quartus II software automatically maps to regional and global clocks
to avoid any restrictions. Enhanced PLLs 5 and 6 drive out to single-
ended pins as shown in Table 1–15. PLLs 11 and 12 drive out to single-
ended pins.
You can connect each fast PLL 1, 2, 3, or 4 outputs (g0, l0, and l1) to either
a global or a regional clock. (PLLs 3 and 4 are not available on Stratix GX
devices.) There is line sharing between clock pins,
FPLLCLK pins, global
and regional clock networks and all PLL outputs. Check Figures 1–21 and
1–22 to make sure that the clocking is valid. The Quartus II software
automatically maps to regional and global clocks to avoid any
restrictions.
FPll7clk
v
FPll8clk
v
FPll9clk
v
FPll10clk
v
Clock Feedback Input Pins
Pll5_fbp/n
v
Pll6_fbp/n
v
Notes to Table 1–14:
(1) This is a fast PLL. The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other
PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
(2) This is an enhanced PLL.
(3) The EP1S40 device in the F780 package does not support PLLs 11 and 12.
Table 1–14. Stratix Clock Input Sources For Enhanced & Fast PLLs (Part 2 of 2)
Clock Input
Pins
All Stratix Devices
EP1S30, EP1S40, EP1S60 &
EP1S80 Devices Only
EP1S40 (3),
EP1S60 &
EP1S80
Devices Only
PLL 1
(1)
PLL 2
(1)
PLL 3
(1)
PLL 4
(1)
PLL 5
(2)
PLL 6
(2)
PLL 7
(1)
PLL 8
(1)
PLL 9
(1)
PLL
10 (1)
PLL
11 (2)
PLL
12 (2)