Altera Stratix - Page 66

1–48 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clocking
Figure 1–21. Global & Regional Clock Connections from Side Clock Pins & Fast PLL Outputs
Notes to Figures 1–21:
(1) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated pin or other PLL
must drive the global or regional source. The source cannot be driven by internally generated logic before driving
the fast PLL.
(2) PLLs 3, 4, 9, and 10 are used for the HSSI block in Stratix GX devices and are not available for this use.
When using a fast PLL to compensate for clock delays to drive logic on
the chip, the clock delay from the input pin to the clock input port of the
PLL is compensated only if the clock is fed by the dedicated input pin
closest to the PLL. If the fast PLL gets its input clock from a global or
regional clock or from another dedicated clock pin, which does not
directly feed the fast PLL, the clock signal is first routed onto a global
clock network. The signal then drives into the PLL. In this case, the clock
delay is not fully compensated and the delay compensation is equal to the
clock delay from the dedicated clock pin closest to the PLL to the clock
input port of the PLL.
For example, if you use CLK0 to feed PLL 7, the input clock path delay is
not fully compensated, but if FPLL7CLK feeds PLL 7, the input clock path
delay is fully compensated.
Figure 1–22 shows the global and regional clock input and output
connections from the fast PLLs. Figure 1–22 shows graphically the same
information as Tables 1–15 and 1–16 but with the added detail of where
each specific PLL output port drives to.
2
CLK0
CLK1
CLK2
CLK3
G0
FPLL7CLK
G1
G2
G3
RCLK0
RCLK1
RCLK4
RCLK5
G10
G11
G8
G9
RCLK9
RCLK8
RCLK15
RCLK14
Global
Clocks
Regional
Clocks
PLL 7
l0
l1
g0
PLL 1
PLL 2
FPLL8CLK
PLL 8
2
CLK10
CLK11
CLK8
CLK9
FPLL10CL
K
PLL 10
PLL 4
PLL 3
FPLL9CLK
PLL 9
Regional
Clocks
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0
l0
l1
g0