Altera Stratix - Default Chapter; Table of Contents

Altera Corporation iii
Contents
Chapter Revision Dates ......................................................................... xiii
About This Handbook ............................................................................. xv
How to Find Information ...................................................................................................................... xv
How to Contact Altera ........................................................................................................................... xv
Typographic Conventions .................................................................................................................... xvi
Section I. Clock Management
Revision History ....................................................................................................................... Section I–1
Chapter 1. General-Purpose PLLs in Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 1–1
Enhanced PLLs ....................................................................................................................................... 1–5
Clock Multiplication & Division .................................................................................................... 1–9
External Clock Outputs ................................................................................................................. 1–10
Clock Feedback ............................................................................................................................... 1–14
Phase Shifting ................................................................................................................................. 1–14
Lock Detect ...................................................................................................................................... 1–15
Programmable Duty Cycle ........................................................................................................... 1–16
General Advanced Clear & Enable Control ............................................................................... 1–16
Programmable Bandwidth ............................................................................................................ 1–18
Clock Switchover ............................................................................................................................ 1–25
Spread-Spectrum Clocking ........................................................................................................... 1–25
PLL Reconfiguration ...................................................................................................................... 1–30
Enhanced PLL Pins ........................................................................................................................ 1–30
Fast PLLs ............................................................................................................................................... 1–31
Clock Multiplication & Division .................................................................................................. 1–34
External Clock Outputs ................................................................................................................. 1–34
Phase Shifting ................................................................................................................................. 1–35
Programmable Duty Cycle ........................................................................................................... 1–36
Control Signals ................................................................................................................................ 1–36
Pins ................................................................................................................................................... 1–37
Clocking ................................................................................................................................................ 1–39
Global & Hierarchical Clocking ................................................................................................... 1–39
Clock Input Connections ............................................................................................................... 1–41
Clock Output Connections ............................................................................................................ 1–43
Board Layout ........................................................................................................................................ 1–50
VCCA & GNDA ............................................................................................................................. 1–50