Altera Stratix - Zbt Sram

3–8 Altera Corporation
Stratix Device Handbook, Volume 2 June 2006
External Memory Standards
clock mode, or K or Kn in single clock mode. The edge-aligned CQ and
CQn clocks accompany the read data for data capture in Stratix and
Stratix GX devices.
Figure 3–5. Data & Clock Relationship During a QDRII SRAM Read Note (1)
Notes to Figure 3–5:
(1) The timing parameter nomenclature is based on the Cypress QDRII SRAM data sheet for CY7C1313V18.
(2) CO is the data clock-to-out time and t
DOH
is the data output hold time between burst.
(3) t
CLZ
and t
CHZ
are bus turn-on and turn-off times respectively.
(4) t
CQD
is the skew between CQn and data edges.
(5) t
CQQO
and t
CQOH
are skew between the C or Cn (or K or Kn in single-clock mode) and the CQ or CQn clocks.
When writing to QDRII SRAM devices, data is generated by the write
clock, while the K clock is 90° shifted from the write clock, creating a
center-aligned arrangement.
f Go to www.qdrsram.com for the QDR SRAM and QDRII SRAM
specifications. For more information on QDR and QDRII SRAM
interfaces in Stratix and Stratix GX devices, see AN 349: QDR SRAM
Controller Reference Design for Stratix & Stratix GX Devices.
ZBT SRAM
ZBT SRAM eliminate dead bus cycles when turning a bidirectional bus
around between reads and writes or between writes and reads. ZBT
allows for 100% bus utilization because ZBT SRAM can be read or written
on every clock cycle. Bus contention can occur when shifting from a write
cycle to a read cycle or vice versa with no idle cycles in between.
ZBT SRAM allows small amounts of bus contention. To avoid bus
contention, the output clock-to-low-impedance time (t
ZX
) must be greater
QA QA + 1 QA + 2 QA + 3
C/K
Cn/Kn
CQ
CQn
Q
t
CO
(2)
t
CO
(2)
t
CLZ
(3)
t
CCQO
(5)
t
CQOH
(5)
t
CQD
(4)
t
CQD
(4)
t
DOH
(2)
t
CHZ
(3)