Altera Stratix - Generating the TXLOADEN Signal

Altera Corporation 5–27
July 2005 Stratix Device Handbook, Volume 2
High-Speed Differential I/O Interfaces in Stratix Devices
Figure 5–19. SERDES Function Timing Diagram with Data-Realignment Operation
Generating the TXLOADEN Signal
The TXLOADEN signal controls the transfer of data between the SERDES
circuitry and the logic array when data realignment is used. To prevent
the interruption of the TXLOADEN signal during data realignment, both k
and v counter are used.
In normal operation the TXLOADEN signal is generated by the k counter.
However, during the data-realignment operation this signal is generated
by either counter. When the k counter is used for realignment, the
×8 clock
×1 clock
D7 D0 D1 D2
D2
D2 D2
D3 D4 D5 D6 D7 D0 D1 D2 D7 D0 D1 D2D3 D4 D5 D6
D3
D3 D3
D4
D4 D4
D5
D5 D5
D6
D6 D6
D7
D7 D7
D0
D0 D0
D1
PD7
Serial data
PD6
PD5
PD4
PD3
PD2
PD1
PD0
D1 D1