Altera Stratix - Chapter 2. Trimatrix Embedded Memory Blocks in Stratix & Stratix GX Devices; Introduction; Trimatrix Memory

Altera Corporation 2–1
July 2005
2. TriMatrix Embedded
Memory Blocks in
Stratix & Stratix GX Devices
Introduction
Stratix
®
and Stratix GX devices feature the TriMatrix™ memory
structure, composed of three sizes of embedded RAM blocks. TriMatrix
memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit
M-RAM blocks, each of which is configurable to support a wide range of
features. Offering up to 10 Mbits of RAM and up to 12 terabits per second
of device memory bandwidth, the TriMatrix memory structure makes the
Stratix and Stratix GX families ideal for memory-intensive applications.
TriMatrix
Memory
TriMatrix memory structures can implement a wide variety of complex
memory functions. For example, use the small M512 blocks for first-in
first-out (FIFO) functions and clock domain buffering where memory
bandwidth is critical. The M4K blocks are an ideal size for applications
requiring medium-sized memory, such as asynchronous transfer mode
(ATM) cell processing. M-RAM blocks enhance programmable logic
device (PLD) memory capabilities for large buffering applications, such
as internet protocol (IP) packet buffering and system cache.
TriMatrix memory blocks support various memory configurations,
including single-port, simple dual-port, true dual-port (also known as
bidirectional dual-port), shift-register, ROM, and FIFO mode. The
TriMatrix memory architecture also includes advanced features and
capabilities, such as byte enable support, parity-bit support, and mixed-
port width support. This chapter describes the various TriMatrix memory
modes and features.
Table 2–1 summarizes the features supported by the three sizes of
TriMatrix memory.
f For more information on selecting which memory block to use, see
AN 207: TriMatrix Memory Selection Using the Quartus II Software.
S52003-3.3