Altera Corporation 10–5
July 2005 Stratix Device Handbook, Volume 2
Transitioning APEX Designs to Stratix & Stratix GX Devices
Architectural Element Names
The architectural element naming system within Stratix and Stratix GX
devices differs from the row-column coordinate system (for example,
LC1_A2, LAB_B1) used in previous Altera device families. Stratix and
Stratix GX devices uses a new naming system based on the X-Y
coordinate system, (X, Y). A number (N) designates the location within the
block where the logic resides, such as LEs within an LAB. Because the
Stratix and Stratix GX architectures are column-based, this naming
simplifies location assignments. Stratix and Stratix GX architectural
blocks include:
■ LAB: logic array block
■ DSP: digital signal processing block
■ DSPOUT: adder/subtractor/accumulator or summation block of the
DSP block
■ M512: 512-bit memory block
■ M4K: 4-Kbit memory block
■ M-RAM: 512-Kbit memory block
Elements within architectural blocks include:
■ LE: logic element
■ IOC: I/O element
■ PLL: phase-locked loop
■ DSPMULT: DSP block multiplier
■ SERDESTX: transmitter serializer/deserializer
■ SERDESRX: receiver serializer/deserializer
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