Altera Stratix - Conclusion

Altera Corporation 2–27
July 2005 Stratix Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Figure 2–16. Mixed-Port Read-During-Write: OLD_DATA
For mixed-port read-during-write operation of the same address location
of a M-RAM block, the RAM outputs are unknown, as shown in
Figure 2–17.
Figure 2–17. Mixed-Port Read-During-Write: DONT_CARE
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value will be unknown during
a mixed-port read-during-write operation.
Conclusion
TriMatrix memory, an enhanced RAM architecture with extremely high
memory bandwidth in Stratix and Stratix GX devices, gives advanced
control of memory applications with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode.
inclock
Port A
data_in
Port A
wren
Port B
data_out
AB
AOld
Port B
wren
B
Address Q
address
A
and
address
B
inclock
Port A
data_in
Port A
wren
Port B
data_out
AB
BUnknown
Port B
wren
Address Q
address
A
and
address
B