Altera Stratix - Chapter 11. Configuring Stratix & Stratix GX Devices; Introduction

Altera Corporation 11–1
July 2005
11. Configuring Stratix &
Stratix GX Devices
Introduction
You can configure Stratix
®
and Stratix GX devices using one of several
configuration schemes. All configuration schemes use either a
microprocessor, configuration device, or a download cable. See
Table 11–1.
This chapter discusses how to configure one or more Stratix or Stratix GX
devices. It should be used together with the following documents:
■ MasterBlaster Serial/USB Communications Cable Data Sheet
■ USB Blaster USB Port Download Cable Development Tools Data Sheet
■ ByteBlaster II Parallel Port Download Cable Data Sheet
■ ByteBlasterMV Parallel Port Download Cable Data Sheets
■ Configuration Devices for SRAM-Based LUT Devices Data Sheet
■ Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet
Table 11–1. Stratix & Stratix GX Device Configuration Schemes
Configuration Scheme Typical Use
Fast passive parallel (FPP) Configuration with a parallel synchronous configuration device or microprocessor
interface where eight bits of configuration data are loaded on every clock cycle.
Passive serial (PS) Configuration with a serial synchronous microprocessor interface or the
MasterBlaster
TM
communications cable, USB Blaster, ByteBlaster
TM
II, or
ByteBlasterMV parallel port download cable.
Passive parallel
asynchronous (PPA)
Configuration with a parallel asynchronous microprocessor interface. In this
scheme, the microprocessor treats the target device as memory.
Remote/local update FPP
Configuration using a Nios
TM
(16-bit ISA) and Nios
®
II (32-bit ISA) or other
embedded processor. Allows you to update the Stratix or Stratix GX device
configuration remotely using the FPP scheme to load data.
Remote/local update PS Passive serial synchronous configuration using a Nios or other embedded
processor. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PS scheme to load data.
Remote/local update PPA Passive parallel asynchronous configuration using a Nios or other embedded
processor. In this scheme, the Nios microprocessor treats the target device as
memory. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PPA scheme to load data.
Joint Test Action Group
(JTAG)
Configuration through the IEEE Std. 1149.1 JTAG pins. You can perform JTAG
configuration with either a download cable or an embedded device. Ability to use
SignalTap
®
II Embedded Logic Analyzer.
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