Altera Stratix - Input;Output Clock Mode

2–18 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Clock Modes
Input/Output Clock Mode
The TriMatrix memory blocks can implement input/output clock mode
for true and simple dual-port memory. On each of the two ports, A and B,
one clock controls all registers for inputs into the memory block: data
input, wren, and address. The other clock controls the block’s data output
registers. Each memory block port also supports independent clock
enables and asynchronous clear signals for input and output registers.
Figures 2–10 and 2–11 show the memory block in input/output clock
mode for true and simple dual-port modes, respectively.