Altera Stratix - Polyphase FIR Interpolation Filters

Altera Corporation 7–17
September 2004 Stratix Device Handbook, Volume 2
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
user needs a way to accept this sample data and send it at a 4r rate to the
input of the DSP block. One way to do this is using a first-in-first-out
(FIFO) memory with input clocked at rate r and output clocked at rate 4r.
The FIFO may be implemented in the TriMatrix memory.
TDM Filter Implementation Results
Table 7–8 shows the results of the implementation of an 18-bit 8-tap TDM
FIR filter as shown in Figure 7–9 on page 7–16.
TDM Filter Design Example
Download the TDM FIR Filter (tdm_fir.zip) design example from the
Design Examples section of the Altera web site at www.altera.com.
Polyphase FIR Interpolation Filters
An interpolation filter can be used to increase sample rate. An
interpolation filter is efficiently implemented with a polyphase FIR filter.
DSP systems frequently use polyphase filters because they simplify
overall system design and also reduce the number of computations per
cycle required of the hardware. This section first describes interpolation
filters and then how to implement them as polyphase filters in Stratix and
Stratix GX devices. See the “Polyphase FIR Decimation Filters” on
page 7–24 section for a discussion of decimation filters.
Interpolation Filter Basics
An interpolation filter increases the output sample rate by a factor of I
through the insertion if I-1 zeros between input samples, a process
known as zero padding. After the zero padding, the output samples in
time domain are separated by Ts/I = 1/(I
× f
s
), where T
s
and f
s
are the
sample period and sample frequency of the original signal, respectively.
Figure 7–10 shows the concept of signal interpolation.
Table 7–8. TDM Filter Implementation Results
Part EP1S10F780
Utilization Lcell: 196/10570 (1%)
DSP Block 9-bit elements: 8/48 (17%)
Memory bits: 360/920448 (<1%)
Performance 240 MHz (1)
Note to Ta b le 7 – 8 :
(1) This refers to the performance of the DSP blocks. The input and output rate is 120
million samples per second (MSPS), clocked in and out at 120 MHz.