Altera Stratix - Section II. Memory; Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices; Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices

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Contents Stratix Device Handbook, Volume 2
VCCG & GNDG .............................................................................................................................. 1–52
External Clock Output Power ...................................................................................................... 1–53
Guidelines ........................................................................................................................................ 1–56
Conclusion ............................................................................................................................................ 1–56
Section II. Memory
Revision History ..................................................................................................................... Section II–1
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 2–1
TriMatrix Memory ................................................................................................................................. 2–1
Clear Signals ...................................................................................................................................... 2–3
Parity Bit Support ............................................................................................................................. 2–3
Byte Enable Support ........................................................................................................................ 2–4
Using TriMatrix Memory ..................................................................................................................... 2–7
Implementing Single-Port Mode .................................................................................................... 2–7
Implementing Simple Dual-Port Mode ......................................................................................... 2–8
Implementing True Dual-Port Mode .......................................................................................... 2–11
Implementing Shift-Register Mode ............................................................................................. 2–14
Implementing ROM Mode ............................................................................................................ 2–15
Implementing FIFO Buffers .......................................................................................................... 2–16
Clock Modes ......................................................................................................................................... 2–16
Independent Clock Mode .............................................................................................................. 2–16
Input/Output Clock Mode ........................................................................................................... 2–18
Read/Write Clock Mode ............................................................................................................... 2–21
Single-Port Mode ............................................................................................................................ 2–23
Designing With TriMatrix Memory .................................................................................................. 2–23
Selecting TriMatrix Memory Blocks ............................................................................................ 2–24
Pipeline & Flow-Through Modes ................................................................................................ 2–24
Power-up Conditions & Memory Initialization ......................................................................... 2–25
Read-During-Write Operation at the Same Address ..................................................................... 2–25
Same-Port Read-During-Write Mode .......................................................................................... 2–25
Mixed-Port Read-During-Write Mode ........................................................................................ 2–26
Conclusion ............................................................................................................................................ 2–27
Chapter 3. External Memory Interfaces in Stratix & Stratix GX Devices
Introduction ............................................................................................................................................ 3–1
External Memory Standards ................................................................................................................ 3–1
DDR SDRAM .................................................................................................................................... 3–1
RLDRAM II ....................................................................................................................................... 3–4
QDR & QDRII SRAM ...................................................................................................................... 3–6
ZBT SRAM ......................................................................................................................................... 3–8
DDR Memory Support Overview ..................................................................................................... 3–10
DDR Memory Interface Pins ......................................................................................................... 3–11
DQS Phase-Shift Circuitry ............................................................................................................ 3–15