Altera Stratix - Page 67

Altera Corporation 1–49
July 2005 Stratix Device Handbook, Volume 2
General-Purpose PLLs in Stratix & Stratix GX Devices
Figure 1–22. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
Notes to Figures 1–22:
(1) CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL’s inclk0 port.
(2) CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL’s inclk1 port.
G12
G13
G14
G15
RCLK10
RCLK11
RCLK2
RCLK3
G7
G6
G5
G4
RCLK13
RCLK12
RCLK7
RCLK6
PLL 12
L0 L1 G0 G1 G2 G3
CLK7
CLK6
CLK5
CLK4
PLL 6
G0 G1 G2 G3 L0 L1
PLL 11
L0 L1 G0 G1 G2 G3
CLK13
CLK12
CLK14
CLK15
PLL 5
G0 G1 G2 G3 L0 L1
E[0..3]
PLL12_OUT
PLL6_OU
T[3..0]
PLL11_OUT
PLL5_OUT[3..0]
PLL5_FB
PLL6_FB
Global
Clocks
Regional
Clocks
Regional
Clocks
(1)
(2)
(1)
(2)
(2)
(2)(1)
(1)