Altera Stratix - Page 234

5–54 Altera Corporation
Stratix Device Handbook, Volume 2 July 2005
Software Support
Table 5–10 shows the number of channels and fast PLLs in EP1S10,
EP1S20, and EP1S25 devices. Tables 5–11 through 5–14 show this
information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Table 5–10. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1)
Device Package
Transmitter/
Receiver
Total
Channels
Maximum
Speed
(Mbps)
Center Fast PLLs
PLL 1 PLL 2 PLL 3 PLL 4
EP1S10 484-pin FineLine BGA Transmitter
(2)
20 840 5 5 5 5
840 (3) 10 10 10 10
Receiver 20 840 5 5 5 5
840 (3) 10 10 10 10
672-pin FineLine BGA
672-pin BGA
Transmitter
(2)
36 624 (4) 9999
624 (3) 18 18 18 18
Receiver 36 624 (4) 9999
624 (3) 18 18 18 18
780-pin FineLine BGA Transmitter
(2)
44 840 11 11 11 11
840 (3) 22 22 22 22
Receiver 44 840 11 11 11 11
840 (3) 22 22 22 22
EP1S20 484-pin FineLine BGA Transmitter
(2)
24 840 6 6 6 6
840 (3) 12 12 12 12
Receiver 20 840 5 5 5 5
840 (3) 10 10 10 10
672-pin FineLine BGA
672-pin BGA
Transmitter
(2)
48 624 (4) 12 12 12 12
624 (3) 24 24 24 24
Receiver 50 624 (4) 13 12 12 13
624 (3) 25 25 25 25
780-pin FineLine BGA Transmitter
(2)
66 840 17 16 16 17
840 (3) 33 33 33 33
Receiver 66 840 17 16 16 17
840 (3) 33 33 33 33