Altera DE1 - Page 46

DE1 User Manual
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SRAM_ADDR[14]
PIN_R10 SRAM Address[14]
SRAM_ADDR[15]
PIN_T7 SRAM Address[15]
SRAM_ADDR[16]
PIN_Y6 SRAM Address[16]
SRAM_ADDR[17]
PIN_Y5 SRAM Address[17]
SRAM_DQ[0] PIN_AA6 SRAM Data[0]
SRAM_DQ[1] PIN_AB6 SRAM Data[1]
SRAM_DQ[2] PIN_AA7 SRAM Data[2]
SRAM_DQ[3] PIN_AB7 SRAM Data[3]
SRAM_DQ[4] PIN_AA8 SRAM Data[4]
SRAM_DQ[5] PIN_AB8 SRAM Data[5]
SRAM_DQ[6] PIN_AA9 SRAM Data[6]
SRAM_DQ[7] PIN_AB9 SRAM Data[7]
SRAM_DQ[8] PIN_Y9 SRAM Data[8]
SRAM_DQ[9] PIN_W9 SRAM Data[9]
SRAM_DQ[10] PIN_V9 SRAM Data[10]
SRAM_DQ[11] PIN_U9 SRAM Data[11]
SRAM_DQ[12] PIN_R9 SRAM Data[12]
SRAM_DQ[13] PIN_W8 SRAM Data[13]
SRAM_DQ[14] PIN_V8 SRAM Data[14]
SRAM_DQ[15] PIN_U8 SRAM Data[15]
SRAM_WE_N PIN_AA10 SRAM Write Enable
SRAM_OE_N PIN_T8 SRAM Output Enable
SRAM_UB_N PIN_W7 SRAM High-byte Data Mask
SRAM_LB_N PIN_Y7 SRAM Low-byte Data Mask
SRAM_CE_N PIN_AB5 SRAM Chip Enable
Table 4.17. SRAM pin assignments.
Signal Name FPGA Pin No.
Description
FL_ADDR[0] PIN_AB20 FLASH Address[0]
FL_ADDR[1] PIN_AA14 FLASH Address[1]
FL_ADDR[2] PIN_Y16 FLASH Address[2]
FL_ADDR[3] PIN_R15 FLASH Address[3]
FL_ADDR[4] PIN_T15 FLASH Address[4]
FL_ADDR[5] PIN_U15 FLASH Address[5]
FL_ADDR[6] PIN_V15 FLASH Address[6]
FL_ADDR[7] PIN_W15 FLASH Address[7]